Research on Adaptive-Bias Technique for K-Band CMOS Power Amplifier
Date Issued
2011
Date
2011
Author(s)
Tsai, Tzung-Chuen
Abstract
In this thesis, a new adaptive-bias technique is proposed to enhance the back-off efficiency of the K-band CMOS power amplifiers. This technique uses a transistor to be a variable resistor which is automatically adjusted by the input power. The operation detail of the adaptive-bias circuit is investigated, and the comparison of this new technique and the other previously reported adaptive-bias techniques is provided. The characteristics of the adaptive-bias circuit are analyzed and are optimized for the performance of power amplifiers. Besides, the limitation and the adjustable range of this adaptive-bias technique are also mentioned in the analysis.
A K-band power amplifier with the proposed adaptive-bias technique is fabricated in 0.18-um CMOS technology. According to the measurement, the proposed PA only consumes 58.6 mW at quiescent state and has 8.7% at the power of 6-dB back-off from P1dB. Compared with the fixed-bias Class-A PA that consumes 90 mW at quiescent state, the proposed PA saves 35% power consumption. The power-added-efficiency at OP1dB is 14% while maintaining 9-dB small-signal gain, 13.9-dBm OP1dB and 15.8-dBm Psat. It is the highest efficiency at the power of 6-dB back-off from P1dB among the reported 0.18-um CMOS power amplifiers above 20 GHz.
Subjects
Power Amplifier
PA
Back-Off Efficiency
K-band
Adaptive-Bias Technique
Type
thesis
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