Low voltage CMOS low noise amplifier using the planar interleaved transformer
Journal
Electronics Letters
Journal Volume
37
Journal Issue
8
Pages
497-498
Date Issued
2001-04
Author(s)
Chih-Chun Tang
Abstract
A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. A planar-interleaved transformer is used to couple the RF signal between cascode transistors in a conventional LNA topology. Based on the modified RF MOS model, a 5.2 GHz CMOS LNA with fully on-chip input/output matching was designed to verify the low-voltage LNA architecture. The measurement results show that it can be operated with 1 V supply voltage.
SDGs
Type
journal article