A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS
Journal
2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Pages
81-84
Date Issued
2015
Author(s)
Abstract
A 0.6V 10-bit 150MS/s single-channel asynchronous subranging SAR ADC using a settling-time relief technique is presented. The technique extends the allocated DAC settling time with the assistance of a coarse ADC and minimizes digital loop delay so that it can reach high speed and low power at a 0.6V supply. This ADC consumes 0.264mW at 150MS/s in 40nm CMOS technology. It achieves an SNDR of 50.5dB at Nyquist rate and results in an FoM of 6.4fJ/c.-s. The core circuit only occupies an area of 0.0063 mm 2 .
Type
conference paper