A Low Power Pipeline ADC Using Time-Domain Transfer Technique

This thesis proposes a 10bit, 300MHz pipeline ADC. Due to the design difficulty in advanced process and large power consumption of operation amplifier(opamp). The proposed work wants to avoid using operation amplifier. At the same time, the time resolution in advanced process becomes more accuracy. So the time domain signal rather than voltage domain signal is used in the proposed work to do the signal process. Normally, the input signal and reference voltage is subtracted in voltage domain. In this thesis, the subtraction is realized in time domain to avoid the overshoot problem due to the delay of comparator. The active area of the proposed work is about 0.694mm2. The ENOB can reach 9.49bit in post-simulation, whose power consumption is 5.2mW and FoM is 22fJ/conversion-step. Unfortunately, the noise of the proposed work was not carefully considered. So, the performance of chip is limited under 5bit. With these problem, the noise analysis and evolve way will be discussed in the thesis.