A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems
Journal
Journal of Parallel and Distributed Computing
Journal Volume
72
Journal Issue
11
Pages
1433-1441
Date Issued
2012
Author(s)
Abstract
Current on-chip network and inter-chip interconnection are designed separately. However, this traditional design methodology faces a great challenge: in a multi-chip system, each many-core chip contains hundreds or thousands of processors. The increasing number of on-chip processors must share one input/output unit to interface with the inter-chip interconnection. The increased network usage at the chip interface may create an uneven traffic load in the on-chip network. That is, traffic jams could occur in the chip area around the input/output unit. New technologies, such as through silicon via and silicon interposer, can directly connect networks on chips. These technologies can improve communication performance and reduce power consumption by omitting the input/output unit. This paper proposes a novel routing scheme to deal with the network scalability issues related to the many-core and multi-chip system-in-package paradigm. The proposed scheme can also enhance the fault-tolerance of nano-scale communication in deep-submicron designs. © 2012 Elsevier Inc. All rights reserved.
Subjects
Fault-tolerance; Many-core; Multi-chip; Network routing; Scalable system; System-in-package
SDGs
Other Subjects
Chip areas; Chip interfaces; Communication performance; Deep sub-micron; Design Methodology; Fault-tolerant networks; Input/output; Inter-chip; Many-core; Multi-chip; Nano scale; Network scalability; Network usage; Networks on chips; On chips; On-chip networks; Routing scheme; Scalable systems; System in package; Through-Silicon-Via; Traffic jams; Traffic loads; Communication; Emergency traffic control; Network routing; Routing protocols; Traffic congestion; Fault tolerance
Type
journal article