Timing is Everything: Power Delivery, Signal Integrity, and Temperature (1/3)
Date Issued
2004-10-31
Date
2004-10-31
Author(s)
DOI
922220E002019
Abstract
Due to coupling noises, process avariations, and
power delivery fluctuations, design uncertainties of on-chip global
interconnect systems rise sharply with deep-sub-micron (DSM)
technology. It is increasingly difficult to assume deterministic
and error-free signal transmission over global wires. Instead,
on-chip global interconnect wires must be analyzed as an errorprone
communication channel characterized by probability of
bit error, and statistical timing distributions. In this paper, a
novel statistical timing analysis approach is developed to analyze
the behavior of two practically important pipelined multiple
clock-cycle global interconnect architectures, namely, the flipflop
inserted global wire and the latch inserted global wire. We
present analytical formula that are based on parameters obtained
using Monto Carlo simulation. These results enable a global
interconnect designer to explore design trade-offs between clock
frequency and probabilty of bit-error during data transmission,
and to evaluate cost-effectiveness of reliability enhancement
measures such as bus coding.
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
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