A Methodology for Generating Bus Wrapper Automatically
Date Issued
2005
Date
2005
Author(s)
Chung, Yi-Chun
DOI
en-US
Abstract
As time-to-market pressures and chip complexities growing, current design tools and methodologies are inadequate for developing million gates System-On-Chip (SOC). If we intend to develop SOC designs more quickly, a reliable scheme to reuse Intellectual Properties (IP) cores is the important issue, and on-chip communication is considered a key technology for this. In this thesis, I propose a new methodology to design the bus wrapper interface and generate it automatically. Because the bus wrapper is able to transfer the interface between different protocols, it can not only achieve the goal of IP reuse but also reduce the complexity when a new IP component intends to connect SOC platforms. In our methodology, we choose the Field Programmable Gate Array (FPGA) board which has Advanced High Performance (AHB) bus system as the experiment platform and connect our bus wrapper with the different IP cores on the board as the case study. Finally, in order to reduce hardware overhead and designers’ efforts, I develop a program to generate the wrapper interface automatically. This program can produce a suitable perfect wrapper interface for each application by entering some parameters which contain the necessary information of IP cores such as protocol type, bit width and data dependant or not.
Subjects
單晶片系統
矽智財
包裝器
SOC
IP Reuse
Wrapper
Type
thesis