Implementation of Software-Based Resolver Emulator with FFSOGI-PLL on DSP for Automotive PHIL Validation
Journal
IFEEC 2025 - Proceedings of the 2025 International Future Energy Electronics Conference
Start Page
336
End Page
341
ISBN (of the container)
979-833154947-3
Date Issued
2025-12-24
Author(s)
Chen, Min-Hong
Abstract
This paper introduces a digital resolver emulator that employs the FFSOGI-PLL to correct phase discrepancies caused by hardware, ADC acquisition, and filtering delays in the electric motor emulator (EME) system for automotive power hardware-in-the-loop (PHIL) validation. The proposed method accurately reconstructs the excitation signal, minimizing distortions due to noise in ADC sampling. Both simulations and experimental results confirm the efficacy of this approach. Comparative studies have shown that carrier signal distortion adversely affects demodulation stability, resulting in suboptimal steady-state performance. These results highlight the significant potential of the digital resolver emulator to improve system accuracy and reliability in PHIL applications.
Event(s)
2025 International Future Energy Electronics Conference, IFEEC 2025
Subjects
digital-to-resolver converter (DRC)
electric motor emulator (EME)
FFSOGI-PLL
power hardware-in-the-loop (PHIL)
resolver emulator
Publisher
IEEE
Type
conference paper