A Frequency Synthesizer for UWB Application
Date Issued
2007
Date
2007
Author(s)
Fan, Che-Wei
DOI
en-US
Abstract
In recent years, wireless communication act as a significant component in data transmission for consumer application. Ultra-Wideband (UWB) system is the next generation of wireless communication aimed to high transmission rate (480 Mbps) over short range (10m) and low power consumption. The MultiBand Orthogonal Frequency Division Multiplexing (MB-OFDM) proposed by the MultiBand OFDM Alliance (MBOA) seems to be mainly adopted. However, one of the most difficult challenges in MB-OFDM UWB system is frequency synthesizer.
Although MBOA partitions the spectrum from 3 to 10 GHz into 14 bands with spacing of 528MHz, “Mode-1” composed of bands 1-3 has the highest economic value for market. The Single-Sideband (SSB) mixing architecture is commonly adopted although some different solutions are published. In this thesis, we develop the different architectures of MB-OFDM Mode-1 frequency synthesizer based on SSB mixer. Meanwhile, CMOS technology is chosen to implement the circuits for high-level integration and low-cost requirement.
We propose the frequency synthesizer based on single PLL to eliminate the use of multiple PLLs, and it can significantly decrease the die area caused by loop filters. Meanwhile, the coupled VCO and coupled injection-locked divider can save the power consumption. Fabricated in TSMC 0.18μm CMOS process, the frequency synthesizer has -36dBc in-band spur performance with 65mW power consumption. For TSMC 0.13μm CMOS process, we furthermore propose multiply-by-1.5 circuit with current-reuse technique to less power dissipation and remove the use of inductor. In this chip, the power dissipation is 31.2mW and the in-band spur is -40dBc.
We propose another frequency synthesizer which is fit to transceiver integration by combining one PLL and one DLL. It can reduce power consumption by the digital type divider, the delay locked loop with modified current-starved delay cells, and our proposed multiply-by-2 circuit. With 65nm CMOS process, the simulation results show our proposed work consumes 19.2mW and it has the lowest power-consumption among the published works.
Subjects
頻率合成器
超寬頻系統
frequency synthesizer
UWB system
Type
thesis
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