Decision feedback equalizers using back-gate feedback technique
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
58
Journal Issue
12
Pages
897-901
Date Issued
2011-12
Author(s)
Chang-Lin Hsieh
Abstract
A merged adder/D-type flip-flop (DFF) is presented by using the back-gate feedback technique. By using this merged adder/DFF, a slicerless one-tap decision feedback equalizer (DFE) and a cascaded DFE are fabricated in 65-nm CMOS technology. For a cable loss of 12 dB and a 30-Gb/s pseudorandom bit sequence (PRBS) of $2 {7} - 1$, the measured bit error rate of the slicerless one-tap DFE is below $10-11. Its power dissipation is 27 mW from a 1-V supply. For a cable loss of 12 dB and a 30-Gb/s PRBS of $2 {15} - 1$ , the measured bit error rate of the cascaded DFE is below $10-12. This cascaded DFE consumes 55 mW from a 1-V supply. © 2006 IEEE.
Subjects
Back gate; Channel loss; Decision feedback equalizer (DFE); Feedback; Intersymbol interference (ISI)
Other Subjects
Adders; Bit error rate; Cables; Feedback; Flip flop circuits; Back gates; Channel loss; CMOS technology; Feedback techniques; Pseudo random bit sequences; Decision feedback equalizers
Type
journal article