A Communication Overhead and Load Balanced Awarearallel ATPG
Date Issued
2009
Date
2009
Author(s)
Yeh, Kuen-Wei
Abstract
Automatic test pattern generation is known to be an NP hard problem. To solveuch a time-consuming problem, many techniques have been proposed to speed upTPG (automatic test pattern generation) engines. This thesis proposes a parallelTPG methodology to speed up test generation process.he proposed methodology distributes the overall fault list among N processorsnd each processor generates test patterns for its own fault list. We call this approachs static fault partitioning. The main considerations of fault partitioned ATPG withistributed memories include keeping low communication overhead and avoiding testattern inflation. To avoid test pattern inflation, an efficient static fault partitioninglgorithm is proposed. On the other hand, to reduce inter-process communicationverhead, the mater-slave architecture is adopted and a smart dynamic load balancingechnique is also proposed.he proposed technique is validated using ISCAS89, ITC99 benchmark circuitsnd a modern industry design.
Subjects
ATPG
parallel
Type
thesis
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