The Design of Phase-Locked Loop Using Capacitive Multiplication Technique and Its Applications
Date Issued
2004
Date
2004
Author(s)
Lee, Sheng-Chou
DOI
en-US
Abstract
Today System-on-Chip (SoC) is a mainstream for integrated-circuit design. Phase-locked loops (PLL) or applications based on PLL are essential for SoC. As we know, when the CMOS process is improved, the transistor size becomes much smaller but not for on-chip passive components. A low-pass filter (LPF) is one of the blocks in PLL, and it is composed by resistors and capacitors. In the past years, a LPF is always designed off-chip to reduce the chip size and save production costs. Nowadays, a LPF integrated into the chip is preferred for SoC. However, these passive components will occupy large area in the chip. If we want to reduce the area occupied by these passive components, the capacitive multiplication techniques proposed in this thesis will solve this problem.
Chapter 2 will give basic ideas of phase-locked loops (PLLs). Noise performances are discussed then to derive proper design flows. A rough design flow is described along with detailed parameter setting.
In chapter 3, three kinds of loop filters with capacitive multiplication technique are introduced at first, and then the behavior simulations are taken to compare with traditional 2nd-order loop filter. Then, a PLL fabricated in CMOS 0.35-µm 1P4M process is presented to verify the capacitive multiplied function.
Chapter 4 presents the SSCGs using capacitive multiplication technique mentioned in chapter 3 and this chapter. One fabricated in CMOS 0.35-µm 2P4M process uses a new capacitive multiplication technique to integrate the LPF into chip, and the other fabricated in CMOS 0.35-µm 1P4M process is based on the architecture mentioned in chapter 3. The spread spectrum function is achieved by modulating the control voltage of the VCO.
In chapter 5, a PLL with fast locking technique is implemented in CMOS 0.35-µm 2P4M process. The proposed PLL achieves fast locking function by a frequency detector added into the PLL. In addition, we propose a new modified FD which can reduce the locking time at most by about 84%.
Subjects
快速鎖定
電容放大技術
鎖相迴路
capacitive multiplication technique
fast locking
phase locked loop
Type
thesis
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