A 10 GHz phase-locked loop with a compact low-pass filter in 0.18 μm CMOS
Journal
IEEE Microwave and Wireless Components Letters
Journal Volume
19
Journal Issue
10
Pages
659-661
Date Issued
2009
Author(s)
Abstract
In this letter, a multi-gigahertz phase-locked loop (PLL) with a compact low-pass filter is presented. By using a novel dual-path control in the PLL architecture, the capacitance in the loop filter can be effectively reduced for high-level integration while maintaining the required loop bandwidth. Consequently, the noise resulted from off-chip components is therefore eliminated, leading to lower timing jitter at the PLL output waveforms. In addition, the timing jitter is further suppressed due to the use of decomposed phase and frequency detection. Based on the proposed techniques, a 10 GHz PLL is implemented in 0.18 mum CMOS for demonstration. Consuming a dc power of 113 mW from a 1.8 V supply, the fabricated circuit exhibits a locking range from 10.1 to 11 GHz. At an output frequency of 10.3 GHz, the measured peak-to-peak and rms jitter are 3.78 and 0.44 ps, respectively.
SDGs
Type
journal article