Multiple voltages scheduling and partitioning scheme for low power design
Date Issued
2004
Date
2004
Author(s)
Cheng, Shih-Yang
DOI
en-US
Abstract
A multiple scheduling method is one of the useful techniques for low power high level synthesis which replaces functional units with lower supply voltage. The thesis presents a scheduling scheme combining with partitioning that minimizes power consumption. This scheme takes power consumption of interconnection into account to keep balance between functional units and interconnection. The timing constrained scheduling method is achieved by performing simulated annealing which is an iterative and non-deterministic algorithm that allows uphill moves to escape from local optima. The proposed algorithm consists of two phases, the initial partition and modification process. In the first phase, the initial solution is decided according to list-based scheduling algorithm. In the next stage, two types of modification are introduced during the process of the simulated annealing. One modification is replacement which moves operation from one partition to another. The other is exchange which exchanges operations in different partitions. A power reduction of 20~40% is shown with strict timing constraint.
Subjects
低功率
多電壓
排程
multiple voltages
schduling
low power
Type
thesis
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