Analog maximum, median and minimum circuit
Resource
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Journal
Circuits and Systems, 1997. ISCAS '97.
Pages
-
Date Issued
1997-06
Date
1997-06
Author(s)
DOI
N/A
Abstract
In this paper, we present a new analog maximum, median and minimum circuit with a new preamplifier. This circuit can be used for sorting multiple-input analog signals. The median circuit has been implemented in a 0.8 /spl mu/m single-poly double-metal (SPDM) CMOS process. The measured output error of this median circuit is less than 2.5 mV. Its frequency response can be up to 1 MHz. The maximum and minimum circuit are also verified by simulation. The experimental and simulation results confirm with the theoretical analysis.
SDGs
Type
journal article
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