Temperature-Aware Placement for SOCs
Resource
Vol. 94, No. 8, August 2006 | Proceedings of the IEEE
Journal
Vol. 94
Journal Issue
No. 8
Pages
-
Date Issued
2006-08
Date
2006-08
Author(s)
Tsai, Jeng-Liang
Chen, Charlie Chung-Ping
Chen, Guoqiang
Goplen, Brent
Qian, Haifeng
Zhan, Yong
Kang, Steve Sung-M
Wong, Martin D.F.
Sapatnekar, Sachin S.
DOI
246246/200611150121559
Abstract
Dramatic rises in the power consumption and
integration density of contemporary systems-on-chip (SoCs)
have led to the need for careful attention to chip-level thermal
integrity. High temperatures or uneven temperature distributions
may result not only in reliability issues, but also timing
failures, due to the temperature-dependent nature of chip
time-to-failure and delay, respectively. To resolve these issues,
high-quality, accurate thermal modeling and analysis, and
thermally oriented placement optimizations, are essential prior
to tapeout. This paper first presents an overview of thermal
modeling and simulation methods, such as finite-difference
time domain, finite element, model reduction, random walk,
and Green-function based algorithms, that are appropriate for
use in placement algorithms. Next, two-dimensional and threedimensional
thermal-aware placement algorithms such as
matrix-synthesis, simulated annealing, partition-driven, and
force directed are presented. Finally, future trends and
challenges are described.
Subjects
Physical design
placement
thermal analysis
thermal simulation
Publisher
Taipei:National Taiwan University Dept Chem Engn
Type
journal article
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