Timing Macro Modeling for Efficient Hierarchical Timing Analysis.

Journal

2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018

Pages

714

Date Issued

2018

Author(s)

Jiang, Iris Hui-Ru

Lee, Pei-Yu

DOI

URI

URL

Type

conference paper