Lithography Friendly Multilevel Analytical Placement
Date Issued
2009
Date
2009
Author(s)
Chao, Wen-Chi
Abstract
Due to the sub-wavelength lithography, manufacturing requires intensive use ofesolution-Enhancement Techniques (RETs), among which Optical Proximity Cor-ection (OPC) is the most popular technique in industry, to improve printability.oreover, physical design for manufacturability becomes the major trend in theesign flow to assist the success of manufacturing.n this thesis, we propose the first lithography friendly multilevel analyt-cal placement considering OPC. We first generate a cell-to-cell lithography costodel based on post-OPC lithography simulation, and then use this model to guideur placement. Based on the multilevel analytical placement framework, we use probability-based cost estimation model for the clustering process, and a ratio-ased cost estimation model for the spreading process, to estimate lithography cost.he clustering and spreading processes are adjusted by our cost estimation models.ith the information provided by our model, our global placement is able to gen-rate a low lithography cost result for the next stage. Then legalization aligns cells to nearby rows considering lithography cost. Finally, detailed placement simultane-usly optimizes lithography cost and wirelength.e test our approach on ISCAS benchmark circuits [2] and ISPD04 IBMenchmark circuits [1]. Based on the experimental results, our lithography friendlyetailed placement alone can already achieve 15.06% and 36.86% lithography costeduction. The results are 13.94% and 34.01% better on printability than the pre-iously proposed detailed placement algorithm－Multiple-Row Optimization Algo-ithm [12], which is the most effective algorithm in the literature. To examine theffectiveness of our approach, we apply different placement flows and compare theesults with the un-lithography-aware wirelength-driven NTUplace3 [6]. The effec-iveness of each stage and the positive impacts between different stages are observedrom the results. By applying the complete flow (which has the highest quality onrintability) of our lithography friendly placement, we can achieves 20.86% and0.94% lithography cost reduction on ISCAS benchmark circuits [2] and ISPD04BM benchmark circuits [1], respectively, comparing with wirelength-driven NTU-lace3, with only less than 3% wirelength overhead. The results show that ourpproach can effectively achieve significant improvements on printability, which hashe best results among all the related works, without notable wirelength qualityecrease.
Subjects
placemet
lithography
multilevel
analytical
OPC
manufacturability
Type
thesis
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