A 900-MHz Bandpass Delta-Sigma Modulator with a Digitally-Assisted Loop Filter
Date Issued
2009
Date
2009
Author(s)
Chen, Yu-Yu
Abstract
This thesis presents the design and circuit implementation of a fourth-order continuous-time bandpass delta-sigma ADC with only two non-return-to-zero (NRZ) feedback DACs and a digitally-aided loop filter, to replace the four original feedback paths. The goal of this work is to reduce the effect of clock jitter in RF delta-sigma ADC. This ADC applies for direct digitization of the RF signal at the 900-MHz center frequency by using the 3.6-GHz sampling frequency. A prototype modulator is fabricated in 0.13-um CMOS process. A CMOS implementation of the modulator provides the feasibility of integrating the following DSP blocks on the same chip. Measurement results of this ADC show the SNR of 67 dB in signal bandwidth of 200 kHz around 900-MHz frequency, while the whole ADC consumes 42.5 mA from 1.2-V supply voltage. newly proposed prototype which can tolerate excess-loop delay to at most one period without any compensated path is described in the second part of this thesis. It is based on the idea that placing a zero to compensate the phase caused by loop delay in a negative feedback system. The realization of this zero is in digital domain, and part of the noise transfer function (NTF) in the analog domain is pushed to the digital domain to reduce the time-constant shifts in analog circuit. Moreover, the number of required DAC units is reduced, and the simple logic implementation of the compensation digital filter provides implicit DAC randomization. System simulation results display the effectiveness of the proposed model.
Subjects
Bandpass Delta-Sigma Modulator
Type
thesis
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