A Parallel Pipelined Implementation for JPEG-LS Encoders
Date Issued
2009
Date
2009
Author(s)
Lin, Chia-Hsiang
Abstract
JPEG-LS is an international standard for lossless and near-lossless image compression. In this paper, a hardware implementation using Verilog HDL is proposed for a JPEG-LS encoder. The hardware design for the JPEG-LS encoder is tested in a Field Programmable Gate Array (FPGA). JPEG-LS Encoders have two main data compression modules, Regular mode and Run mode. We separate some modules such as Line Buffer, Regular mode, Run mode, Golomb Encoder, and update parameters from each other. We also share the module parameters to reduce the gate number. The architecture developed is a pipelined parallel design, which can speed up 13~15% the JPEG-LS encoder compression performance.
Subjects
Parallel
Pipeline
Type
thesis
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