Design Automation for a-IGZO Thin Film Technology Using a Multi-Row Standard Cell Architecture
Journal
Proceedings - 2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025
Start Page
1
End Page
5
ISBN (of the container)
979-833158907-3
Date Issued
2025-10-12
Author(s)
Lin, Yi-Ting
Tang, Yalun
Kang, Byeonggon
Nomura, Kenji
Lo, Yuhwa
Chang, Lifu
Lin, Bill
Cheng, Chung-Kuan
Abstract
Amorphous-IGZO thin-film transistors (a-IGZO TFTs) have attracted increasing attention for emerging applications in wearable devices and IoT technologies, owing to their compatibility with flexible substrates, low processing temperatures, and energy-efficient operation. However, the lack of p-type devices breaks the symmetry of conventional CMOS logic, and the technology requires a double-gate structure with bias voltage to adjust the I-V characteristics. While previous studies have primarily focused on fabrication and application aspects, the electronic design automation (EDA) perspective remains underexplored. In this paper, we propose the first standard cell synthesis framework for a-IGZO TFTs. The framework features a cell layout architecture that integrates bias voltage into power rail planning and adopts multirow transistor placement to address logic asymmetry. Transistor placement is modeled as an exact cover with colors (XCC) problem and solved using the dancing cells algorithm, while intra-cell routing is formulated with satisfiability modulo theories (SMT) to account for double-gate and multi-rail structures. Experimental results demonstrate the effectiveness of the proposed architecture and methodologies. © 2025 IEEE.
Event(s)
2025 21st IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2025
Publisher
IEEE
Type
conference paper