Test Pattern Generation for Maximum Circuit Delay under Simultaneous Input Transition Model
Date Issued
2007
Date
2007
Author(s)
Lee, Chen-Hao
DOI
en-US
Abstract
In this thesis, we propose a new timing analysis method which is different from traditional ones. Our method consists of several steps：(1) We use static timing analysis (STA) to find out an initial critical path in the circuit. (2) We perform false path checking on the critical path by the Boolean Satisfiability (SAT) engine. (3) If the critical path is a true path (i.e. not false), we will try to push the delay bound obtained in the STA process by considering simultaneous input transitions of the circuit. (4) If we get certain input patterns from SAT engine, then we can evaluate the new delay data by dynamic timing analysis (DTA). In this way we can get an accurate delay bound and solve the circuit false path problem at the same time. Moreover, because we only simulate several input patterns in the circuit, the performance of our method must be better than traditional DTA. In our experiments, we demonstrate that our method can achieve both better performance and accuracy than random simulation. Finally we believe that the test patterns we derive by the SAT engine would be useful and important to the post-layout timing simulation stage.
Subjects
靜態時序分析
動態時序分析
多重變換
測試訊號
布林限制
可滿足性問題
STA
DTA
multiple transitions
test patterns
Boolean constraints
SAT
Type
thesis
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