Intelligent process diagnosis based on end-of-line electrical test data
Resource
Electronics Manufacturing Technology Symposium, 1996., Nineteenth IEEE/CPMT
Journal
Electronics Manufacturing Technology Symposium, 1996.
ISBN
0-7803-3642-9
Date Issued
1996-10
Date
1996-10
Author(s)
Abstract
This paper describes a model for yield learning in integrated circuit package assembly. This model provides a management tool for yield projection, resource allocation and what-if analysis. An Excel spreadsheet-based model was developed using a series of case studies of TCP, PQFP, CBGA, and PBGA packages entering manufacturing. The factors that affect yield learning rates (e.g. process complexity, production volumes, personnel experience) were identified and models successfully built to predict the yield ramp for each product. We found that a common model with a common set of factors and the same relative factor importance could be used for all package technologies.
SDGs
Type
conference paper
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