Power Estimation for Embedded Processors based on Verilog-to-SystemC Conversion
Date Issued
2008
Date
2008
Author(s)
Chuang, Feng-Hsu
Abstract
With the growing demand of the portable devices in recent years, battery life and power consumption have become important in the design of embedded systems. While the Verilog HDL is popular for hardware engineers to design chips, it is very time-consuming to using Verilog HDL for power analysis. One would prefer to use a higher level system design language, e.g. SystemC, to evaluate and model the power consumption of a system in an early design stage.n this thesis, we choose to study Simply RISC, an open source chip design, based on Sun UltraSPARC T1, and proposed a power estimation scheme based on Verilog-to-SystemC conversion. Given a program, the scheme reports the information of power consumption for the converted SystemC module, with up to the 15X speedup over Verilog HDL-based simulation, while the estimated power is within 1.53% of the result from a Verilog HDL simulation tool.
Subjects
conversion
power estimation
Type
thesis
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