Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systems
Journal
2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
Date Issued
2013
Author(s)
Abstract
Network-on-Chip (NoC) systems achieve higher performance than bus systems for chip multiprocessor (CMP) systems. However, as the complexity of network increases, routing problems become performance bottlenecks. Conventional routings only use local or regional buffer occupancy (BO) information to choose a better path to deliver a packet. Due to lack of path diversity (PD) information, which is global information, these routings are difficult to spread traffic to different paths for load balancing. Therefore, in this paper, we present a latency prediction model to simultaneously consider PD and BO information. Based on this model, this work proposes Hybrid Path-Diversity-Aware (Hybrid PDA) adaptive routing to overcome congestion problem in NoC. Experiments with different scenarios are conducted. The simulation results show that the proposed selection has a considerable latency reduction over other selection functions, with up to 94.6%, and has better scalability in large scale NoC.
Type
conference paper