A 10Gb/s Equalizer with a Digital Adaptive Algorithm
Date Issued
2014
Date
2014
Author(s)
Hsiao, Jui-Cheng
Abstract
An equalizer using a digital adaptive algorithm is proposed to replace RC filters, rectifiers, V/I converters and large loop capacitors. The proposed algorithm uses two analog reference levels to represent the high-frequency and low-frequency components of the input data, respectively. By monitoring the two reference levels, the proposed equalizer can tune its high-frequency gain to compensate the channel loss appropriately. The measured peak-to-peak jitter for the 90-cm channel is reduced from 81.63 ps to 33.84 ps with 8-Gb/s input data; while the 37-cm channel is decreased from 47.64 ps to 37.60 ps with 10-Gb/s input data. The proposed adaptive equalizer successfully operates for different channel lengths (up to 90-cm) on FR-4 PCB. This work has been fabricated in a 40-nm process, and the equalizer core circuit occupies 0.014 mm2 and consumes 10 mW from a 1-V supply (excluding output buffer circuits). The proposed equalizer uses only digital logic gates for adaptation instead of RC filters, rectifiers, V/I converters and large capacitors for loop stabilization. Such digital-intensive implementation can highly reduce the hardware cost in advanced CMOS technologies.
Subjects
自適應性等化器
數位自適應性演算法
Type
thesis
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