Package-strain-enhanced device and circuit performance
Journal
Technical Digest - International Electron Devices Meeting, IEDM
Pages
233 - 236
Date Issued
2004
Author(s)
Abstract
The hole mobility enhancement can be as high as -18% for SiO2 and ∼20% for high-κ HfO2 gate stack dielectrics with the uniaxial compressive strain (0.2%) parallel to the channel. The highest drain current of -22% at saturation and ∼30% at linear region is observed for the bulk Si PMOS with high-K gate stacks. The drain current and hole mobility of bulk Si PMOS are degraded under the small biaxial tensile strain, while substrate-strained Si device shows opposite. The nonoptimized ring oscillator has the speed enhancement of ∼7% under the uniaxial tensile strain parallel to NMOS channel. Proper package strain also gives the drive-current as well as mobility enhancement at 100°C. © 2004 IEEE.
Event(s)
IEEE International Electron Devices Meeting, 2004 IEDM
Other Subjects
Hafnium oxides; High-k dielectric; Hole mobility; Logic gates; Silica; Silicon; Tensile strain; Timing circuits; VLSI circuits; Annealing; Dielectric materials; Doping (additives); Hole mobility; Silicon wafers; Surface roughness; Circuit performance; Compressive strain; Device performance; Drain holes; High-K gate stacks; High-κ; Linear region; Mobility enhancement; Package strain; Uniaxial compressive; Drain current; MOSFET devices; Compressive stain; Dopants; Tensile strain; Thermal budget
Type
conference paper