Self-Heating-Aware Buffered Clock Tree Synthesis
Date Issued
2012
Date
2012
Author(s)
Hsu, Tzu-Hsuan
Abstract
Temperature affects clock signal delays. Without considering temperature effects, clock skew could be significantly increased and chip performance might be accordingly degraded. Most existing temperature-aware clock tree synthesis methods have two major drawbacks. First, since they perform post processes to pre-constructed clock trees, the solution space is often limited. Second, heat generated by a clock tree itself is not considered. As a clock tree consumes substantial dynamic power, the considerable heat generated by itself cannot be ignored. In this thesis, we propose a self-heating-aware buffered clock tree synthesis flow to remedy the drawbacks. A mixed integer linear programming (MILP) formulation is proposed to simultaneously model heat spreading, place buffers, and determine a temperature-aware clock tree topology. In addition, to avoid time-consuming thermal simulations during clock tree construction, a fast superposition approach is proposed to incrementally update thermal profiles. Finally, to reduce runtime, the original MILP formulation is transformed to a succession of low-complexity feasibility problems. Experimental results show that our approach can achieve averagely 50.57% worst-case clock skew reduction. With our proposed speed-up methods, runtime can be further reduced by more than 17.29X.
Subjects
physical design
clock tree synthesis
clock skew
temperature effect
Type
thesis
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