High-Speed Analog Equalizers and Digital Near-End Crosstalk Canceller for Multi-Lane Serial-Link Receivers

As process technologies continue to advance, the operating frequency of processors and memories increases rapidly. This makes the bandwidth of the I/O interface a primary bottleneck in many systems. For example, high-speed data transmission in a wireline communication system suffers from both skin effect and dielectric loss. These frequency-dependent impairments induce a significant inter-symbol interference (ISI) to corrupt the transmitted data and therefore degrade the bit error rate (BER). In order to mitigate the ISI and ameliorate the BER, analog equalizers have been used widely so as to compensate the channel loss. In modern broadband data communications, however, the transmitted data are also impaired by crosstalk interferences when multi-lane serial links become closer.
This dissertation is mainly divided into two parts. High-speed analog equalizers for wireline communication systems are introduced first, followed by a digital near-end crosstalk (NEXT) canceller, especially for multi-lane serial-link receivers. In chapter 2, a 10-Gb/s inductorless analog equalizer is realized in 0.13-μm CMOS technology by using the proposed interleaved active feedback topology. In chapter 3, a 40-Gb/s 14.4-mW analog equalizer is realized in 0.13-μm CMOS technology by using the proposed inductive feedback amplifier. In chapter 4, a 50-Gb/s 10-mW analog equalizer is realized in 65-nm CMOS technology by using the proposed transformer feedback technique. In chapter 5, a 5-Gb/s digital NEXT canceller merged with an analog equalizer is realized in 0.13-μm CMOS technology by using the proposed sign-sign block least-mean-square (SSB-LMS) circuit.
The analog equalizer using the proposed inductive feedback amplifier is the first 40-Gb/s one in 0.13-μm CMOS technology. By using the proposed SSB-LMS circuit, the maximum critical delay of the up/down counters is relaxed to 500 ps rather than 200 ps for the data rate of 5-Gb/s.