A 18.5GHz Fully Differential Phase Lock Loop for 40~48GHz UWB System
Date Issued
2006
Date
2006
Author(s)
Yang, Tz-Cheng
DOI
en-US
Abstract
With the rapid growing of the wireless communication system, the demands of high precision phase-locked loops (PLLs) increase significantly. Besides, output phase noise of PLLs is very important for local oscillator. It is because that the quality of phase noise would influence bith transmitting and receiving chain seriously.
This thesis will aim to implement an 18.5 GHz PLL with improved phase noise for 40~48 GHz UWB system. We will propose two architectures which are a common high speed phase-locked loop and an improved fully differential phase-locked loop. The performance of both architectures will be compared.
Subjects
差動
鎖相迴路
超寬頻
相位雜訊
PLL
UWB
differential
phase noise
jitter
Type
thesis
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