All-digital Clock and Data Recovery and All-digital Phase-locked Loop
Date Issued
2009
Date
2009
Author(s)
Chen, I-Fong
Abstract
In recent years, the orientation of the fabrication process is to shrink the scaling of the transistor. Scaling down the transistor will have less power consumption and faster operation frequency to design circuits. However, it has extra drawbacks for analog circuits, but it is more suitable for digital circuits. Therefore, digital equivalent implementations of analog circuits are more popular, such as the phase-locked loop and the clock and data recovery. In this thesis, a 1.25 Gbps all-digital clock and data recovery is proposed. The clock frequency of the accumulator is too slow. The proposed pre-accumulator and the path with the scaler (the first integral path) are used to slow down the clock frequency of the accumulator and reduce the loop latency. By reducing the loop latency, the smaller is used to have low jitter performance without sacrificing the phase margin. Compared with the loop without the first integral path, it also increases the damping factor and the bandwidth. The jitter of the proposed 1.25Gbps all-digital clock and data recovery is only 51.1 ps and its bit error rate is below 10-12. The power consumption is 23.4 mW and the core area is 0.423mm2. In this thesis, a 1.25 GHz all-digital phase-locked loop is proposed. The bang-bang type all-digital phase-locked loop needs long frequency acquisition time because the phase/frequency detector only has binary outputs, and. The proposed algorithm can effectively reduce the frequency acquisition time. The supply noise toward the DCO has severely impact in the all-digital PLL. Therefore, the proposed bandwidth calibration circuit decides the bandwidth which make the all-digital PLL have the lowest jitter by using the timing window measuring the jitter to change the bandwidth. The jitter of the proposed all-digital phase-locked loop is 38.9 ps and the phase noise is -103.22dBc/Hz at 1MHz offset. Its power consumption is 9 mW and the core area is 0.348mm2.
Subjects
ADCDR
ADPLL
Type
thesis
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