Design and Implementation of a Low Power CMOS RF Transmitter Front-end
Date Issued
2005
Date
2005
Author(s)
Hung, Ping-Hsi
DOI
en-US
Abstract
Recently, the fast-growing market of wireless communication has motivated research and development on related topics all over the world. The current trend of wireless technology focuses on low-cost and high-performance integrated circuits. Typically, a complete wireless communication system can be divided into radio-frequency (RF) front-end, intermediate frequency (IF) module and base-band transceiver. Due to the technology limitation and required system specifications, these modules are normally designed and fabricated in different process technologies. Though the performance of individual modules can be optimized in a multi-chip solution, the issues such as yield, power dissipation and overall system performance have long impeded the development of high-volume and low-cost wireless communication systems.
Fortunately, the possibility of implementing RF circuits using sub-micron CMOS process has been demonstrated with recent advances in semiconductor technology. Integration of RF front-end and base-band digital circuits in a single chip becomes the mainstream of wireless communication industry.
In this thesis, a low-power transmitter amplifier with diode linearizer for 5-GHz short-range wireless applications and an ultra-low power transmitter front-end are presented. The integrated NMOS diode which serves as the function of diode linearizer effectively improves the linearity of the fabricated transmitter amplifier with insignificant increase in chip area. It exhibits an output power of 4.9dBm and a PAE 29% with a power dissipation of 5.1mW at quiescent condition under a 1-V power supply. As for the proposed direct-conversion transmitter (DCT), a novel differential to single-ended converter with driver amplifier (D2S-converter with DA) is introduced, exhibiting an excellent performance on the gain balance and the phase balance. The designed transmitter front-end demonstrates an output power of -1.5dBm @P1dB and conversion gain of 11.4dB, while consuming a dc power of 5.6mW from an ultra-low supply voltage of 0.6 V. The die sizes of two prototypes are 1×0.845 mm2 and 1.09×1.09 mm2, respectively.
Subjects
金氧半
低功率
發射器
射頻
Transmitter
CMOS
low power
RF
Type
thesis
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