VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units
Journal
Proceedings - Design Automation Conference
Journal Volume
2021-December
Pages
1117-1122
Date Issued
2021
Author(s)
Abstract
AI-dedicated hardware designs are growing dramatically for various AI applications. These designs often contain highly connected circuit structures, reflecting the complicated structure in neural networks, such as convolutional layers and fully-connected layers. As a result, such dense interconnections incur severe congestion problems in physical design that cannot be solved by conventional placement methods. This paper proposes a novel placement framework for CNN accelerator units, which extracts kernels from the circuit and insert kernel-based regions to guide placement and minimize routing congestion. Experimental results show that our framework effectively reduces global routing congestion without wirelength degradation, significantly outperforming leading commercial tools. ? 2021 IEEE.
Subjects
Convolutional neural networks
Multilayer neural networks
Traffic congestion
VLSI circuits
AI applications
Circuit structures
Complicated structures
Convolutional neural network
Dedicated hardware
Hardware design
Neural-networks
Routing congestion
Structure-aware
VLSI structures
Convolution
SDGs
Type
conference paper