A variable-length DHT-based FFT/IFFT processor for VDSL/ADSL systems
Resource
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Journal
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Pages
-
Date Issued
2004-12
Date
2004-12
Author(s)
Pao, Tsung-Chieh
Chang, Ching-Chi
Wang, Chorng-Kuang
DOI
N/A
Abstract
A matrix form of the radix-4 Discrete Hartly Transform (DHT) algorithm is derived. And two process element (PE) circuits are proposed for the variable-length application. One is for radix-2 with one real multiplier and three adders, and the other is for radix-4 with one real multiplier and seven adders. The radix-4 DHT processor of variable-length, namely, 8192/4096/2048/1024/512, meets the DMT-VDSL and ADSL requirements. Only six real multipliers, 2.01 N (16467) registers and simple logic circuits are used to perform 8192-points FFT/IFFT in 23 /spl mu/s. Implemented in 0.25/spl mu/m 1P5M typical CMOS technology, the core occupies an active area of 5mm /spl times/ 5mm. Power dissipation is 300mW using a 2.5V supply voltage.
SDGs
Type
journal article
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