Parallel architectures of 3-step search block-matching algorithm for video coding
Resource
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Journal
IEEE International Symposium on Circuits and Systems, 1994. ISCAS '94
Pages
-
Date Issued
1994-06
Date
1994-06
Author(s)
DOI
N/A
Abstract
This paper describes fully pipelined parallel architectures for the 3-step search block-matching motion estimation algorithm. Difficulties of this algorithm in hardware implementation were overcome by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed architectures provide efficient solutions for real-time motion estimations required by various video applications.>
Type
journal article
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