A DfT Technique for Asynchronous Circuit
Date Issued
2008
Date
2008
Author(s)
Cheng, Chi-Hsuan
Abstract
This thesis presents a scan test technique for asynchronous delay-insensitive circuits. A true asynchronous scan chain design is proposed because no clock is needed even in the test mode and scan testing can be done in asynchronous way. Full scan is available and test pattern generation can be performed by combinational automatic test pattern generation tool. Experiments on an 8051 datapath circuit show that the fault coverage is as high as 99.59% and the area overhead is smaller than previous methods. The presented idea is successfully demonstrated in two chips of a-Si TFT technology on the glass substrate. This proposed scan test technique provides a good solution for the asynchronous delay-insensitive circuit applications, such as large area system chip, globally asynchronous locally synchronous system-on-chip, flexible electronics, and system-on-panel etc.
Subjects
Design-for-test
scan test
Asynchronous DfT
Type
thesis
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ntu-97-R95943085-1.pdf
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