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  4. Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs
 
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Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs

Journal
ACM Transactions on Design Automation of Electronic Systems
Journal Volume
28
Journal Issue
5
Date Issued
2023-09-08
Author(s)
Wei, Min
Tong, Xingyu
Wen, Yuan
Chen, Jianli
Yu, Jun
Zhu, Wenxing
YAO-WEN CHANG  
DOI
10.1145/3582554
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/636158
URL
https://api.elsevier.com/content/abstract/scopus_id/85171801157
Abstract
As design complexity keeps increasing, the 2.5D field-programmable gate array (FPGA) with large logic capacity has become popular in modern circuit applications. A 2.5D FPGA consists of multiple dies connected through super long lines (SLLs) on an interposer. Each die contains heterogeneous logic blocks and ASIC-like clocking architectures to achieve better skew and timing. Existing works consider these problems separately and thus may lead to serious timing issues or routing failure. This article presents an analytical placement algorithm for the 2.5D FPGA to simultaneously minimize the number of inter-die SLL signals and intra-die clocking violations. Using a lifting dimension technique, we first formulate the 2.5D global placement problem as a three-dimensional continuous and differential minimization problem, where the SLL-aware block distribution is modeled by 3D Poisson's equation and directly solved to obtain an analytical solution. Then, we further reformulate the minimization problem as a separable optimization problem with linear constraints. Based on the proximal alternating direction method of multipliers optimization method, we efficiently optimize the separable subproblems one by one in an alternating fashion. Finally, clock-aware legalization and detailed placement are applied to legalize and improve our placement results. Compared with the state-of-the-art works, experimental results show that our algorithm can resolve all clocking constraints and reduce the number of SLL crossing signals by 36.9% with similar wirelength in a comparable running time.
Subjects
2.5D heterogeneous FPGAs | Additional Key Words and PhrasesPhysical design | ADMM-based optimization | placement
SDGs

[SDGs]SDG16

Type
journal article

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