Timing-Aware Cache Leakage Control
Date Issued
2006
Date
2006
Author(s)
Chi, Jaw-Wei
DOI
en-US
Abstract
Leakage energy consumption is an increasing important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transistor budget, they are the primary targets for processor leakage reduction. Two types of circuit techniques have been proposed to reduce cache leakage: Gated-Vdd and drowsy caches. Cache lines can be turned into a low-leakage state periodically or being idle for a pre-set number of cycles. Both control policies induce performance unpredictability thereby not suitable for real-time applications. In this thesis, I propose a cache leakage control algorithm for hard real-time applications. I exploit task slack to turn cachelines into the low leakage state. The objective of the proposed algorithm is to achieve leakage reduction while meeting the timing constraint. The proposed scheme can achieve 85.2\% leakage reduction on average while meeting the real-time constraint.
Subjects
快取記憶體
漏電流
即時系統
Cache
Leakage
Real time system
SDGs
Type
thesis
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