Embedded JPEG encoder IP core and memory efficient preprocessing architecture for scanner
Resource
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Journal
The 2000 IEEE Asia-Pacific Conference on Circuits and Systems, 2000. APCCAS 2000
Pages
-
Date Issued
2000-12
Date
2000-12
Author(s)
DOI
N/A
Abstract
In this paper a baseline JPEG encoder soft intellectual property (IP) is proposed together with a memory efficient preprocessing architecture for scanner to solve the bandwidth problem between PC and scanner. This JPEG IP features quantization tables that are reconfigurable at run time and compile time. It is a modularized and fully pipelined design with friendly interface, which makes it easier to be integrated into various application systems. It is silicon proven to run up to 40 MHz at 3.3 V. With the optimized preprocessing unit feeding data smoothly into JPEG core, it is a low cost and competitive solution for a scanner to have a compression function embedded.
SDGs
Type
journal article
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