Low Power Content-Addressable Memory (CAM) Design with Low Voltage Swing Technique Using NOR-Type

This thesis presents a novel VLSI architecture for high speed and low power content addressable memory (CAM) design. CAMs have been widely used in many digital systems. The primary application of CAMs is network routers, that requiring high search speed. Therefore CAMs usually are used in parallel design to maintain the property of high speed operation, but also resulted in serious power consumption.n order to solve the problem, we propose a low voltage swing cell circuit to replace traditional CAM cell. The main purpose is to reduce the matchline voltage swing. Because of charge/discharge voltage swing reduction on the matchline, the charge/discharge current will be reduced during operation cycle. The proposed design can reduce power consumption effectively, in addition to increase the performance. We also design new matchline sense amplifier to avoid the output logic error caused by low swing of the matchline. Finally, we used TSMC 0.18um CMOS technique to simulate the proposed CAM cell. For the proposed structures, the power consumption will be reduced about 35% and have a general and robust application.