Design and Analysis of Wide Bandwidth Frequency Divider and Digital-Calibrated RF Circuit
Date Issued
2012
Date
2012
Author(s)
Kuo, Yen-Hung
Abstract
For wireless high-data-rate communication, the wideband frequency resource which allocate at microwave and millimeter wave frequency is essential. Many applications such as the next generation 4G-LTE backhaul link and the short-range Cloud communications at 60 GHz utilize wide-band frequency resources for high data rate. Therefore, the design of wide-band high-speed local oscillator (LO) is an important issue in today’s wireless transceiver. However, the design of high-speed wide-band LO is not an easy task. The parasitic effect, large division ratio between output frequency and reference frequency, process variation make the bandwidth and speed limited. These design bottlenecks need to be solved in frequency divider which is the key component on the feedback path of frequency synthesizer.
For high-speed operation, the dynamic frequency divider such as injection-locked frequency divider (ILFD) and Miller divider can be used. The dynamic frequency divider has drawback of narrow bandwidth. Therefore, the bandwidth-enhanced techniques proposed in previously published work achieve 42% and 28% bandwidth for ILFD and Miller divider, respectively. Nevertheless, the bandwidth is not wide enough to tolerance the process, voltage, and temperature (PVT) variations. Therefore, the purpose of this dissertation is to develop wideband, large division ratio frequency divider and to develop PVT-tolerant digital-assisted circuit for RF integrated circuits.
To tolerant the PVT variation, the wideband cascoded ILFD and band-switched Miller divider are proposed. Parasitic effect is carefully analyzed in both frequency dividers. In addition to analysis of parasitic, the digital-assisted technique is used in band-switched Miller divider to simplify complexity and to increase speed of the calibration circuit. Furthermore, reliable digital circuit is also integrated with isolator of frequency-modulated continuous wave (FMCW) front-end to demonstrate the performance-enhanced digital calibration.
The first circuit presented in this dissertation, is the wide-band, divide-by-4 frequency divider. A cascoded current-mode logic and ILFD has less parasitic effect and consumes less dc power. The cascoded frequency divider is implemented in 0.13-μm CMOS technology and has a 77.3% frequency locking range from 13.5 to 30.5 GHz at injection power of 0 dBm while consuming 7.3-mW dc power.
A bandwidth-enhanced technique for Miller divider is presented in this dissertation. By detecting the power rather than the frequency, the proposed digital algorithm is high efficiency and is low complexity. The digital-assisted frequency divider is implemented in 0.18-μm CMOS technology which shows 57.4 % bandwidth from 8.2 to 14.8 GHz at input power of 0 dBm while consuming 12-mW dc power.
Finally, a digital-calibrated isolator for FMCW RFIC is described in this dissertation. The proposed transmitter-to-receiver isolator has digital-calibrated circuits to find the optimal attenuation in the feedforward isolator automatically. The proposed isolator is implemented in 0.18-
Subjects
CMOS
injection-locked frequency divider (ILFD)
Miller divider
digital calibrated circuit
isolator
frequency modulated continuous wave (FMCW)
feedforward
current-mode logic (CML)
Type
thesis
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