Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration.
Journal
Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017
Pages
78:1-78:6
Date Issued
2017
Author(s)
Zuo, Wei
Pouchet, Louis-No?l
Ayupov, Andrey
Kim, Taemin
Lin, Chung-Wei
Shiraishi, Shinichi
Chen, Deming
Abstract
A desirable feature of a development tool for SoC design is that, given the important applications in the domain to be targeted by the SoC, a powerful hardware-software partitioning engine is available to determine which function(s) shall be mapped to hardware. However, to provide high-quality partitioning, this engine must be able to consider a rich design space of possible alternate hardware and software implementations for each program region candidate for hardware acceleration, in turn making the task of finding the optimal mapping very difficult given the number of design points to consider and the need for accurate modeling of latency, power and area.
Type
conference paper