An Efficient FPGA-Based Dilated and Transposed Convolutional Neural Network Accelerator
Journal
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Volume
71
Journal Issue
11
Start Page
5178
End Page
5186
ISSN
1549-8328
1558-0806
Date Issued
2024-11
Author(s)
Abstract
This work presents a Field Programmable Gate Array (FPGA)-based deep neural network (DNN) accelerator that can maintain consistently high efficiency when executing various neural network architectures, including convolutional neural network (CNN), transposed and dilated convolution (TD-convolution) operations for modern computer vision (CV) tasks. To deal with the utilization degradation issue with a large processing unit (PE) array, a 3-D mapping strategy that adaptively tailors different layer configurations is proposed to optimize the parallelism dimensions of the PE, which significantly increases the hardware utilization to enhance the accelerator efficiency. Moreover, to minimize the implementation and performance overhead resulting from the TD-convolution operations, a unified processing flow is proposed to realize an integrated operation of traditional and TD-convolution. This allows the accelerator to bypass redundant zero operations, further boosting overall efficiency. The 4096-PE accelerator implementation on Intel Stratix 10 FPGA achieves a throughput performance of 2.597-2.870 TOPS with an efficiency of 0.63-0.70 GOPS/DSP across various DNN networks. This represents 1.72× and 1.73× improvement in throughput and efficiency, respectively, compared to the state-of-the-art designs.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article