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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
A Two-level Test Data Compression and Test Time Reduction Technique for SOC
Details
A Two-level Test Data Compression and Test Time Reduction Technique for SOC
Journal
VLSI/CAD Symposium
Date Issued
2005-01
Author(s)
CHIEN-MO LI
Yu-Te Liaw
CHIEN-MO LI
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/318033
Type
conference paper