Development of Wide-Bandgap Semiconductor Transistors: Amorphous InGaZnO Thin Film Transistors and Enhancement-Mode GaN High Electron Mobility Transistors
Date Issued
2014
Date
2014
Author(s)
Su, Liang-Yu
Abstract
This dissertation focus on developing wide-bandgap semiconductor transistors, including low-noise high-speed amorphous-InGaZnO (a-IGZO) thin film transistors (TFTs) on glass substrate and high voltage enhancement-mode (E-mode) GaN high electron mobility transistors (HEMTs). High speed TFTs can be applied to fabrication of display panel driver circuit, realizing system-on-panel and help to develop low cost radio frequency identification (RFID) tags. Due to the advantages of high breakdown voltage (VBD) and low on resistance (Ron), GaN HEMTs can potential replace Si-based power devices for high-frequency high-efficiency switching mode power supplies.
High-κ dielectrics can effectively reduce the device operation voltage and increase the current density. However, high interface state and small band-gap often induce device instability and higher leakage current. To solve these problems, an HfO2/SiO2 bilayer structure was proposed as the gate dielectric of a-IGZO TFTs. Since high-κ dielectrics can improve the maximum oxide controllable charges and achieve a fully depleted state, device can exhibit low subthreshold swing (SS) of 96mV/decade, high on-to-off ratio of 1.5×1010 and a transfer curve hysteresis lower than 50mV. Next, compared to single-layer HfO2 dielectric, it was proved that HfO2/SiO2 bilayer dielectric can effectively increase carrier mobility, reduce SS, reduce leakage current and increase current on-to-off ratio. Low frequency noise (LFN) characteristics indicate that the main noise source is flicker noise and originate from mobility fluctuation. In addition, the a-IGZO TFTs with HfO2/SiO2 bilayer dielectric can achieve a low Hooge’s parameters of 2×10 -3, which is the least noisy oxide TFTs on glass substrate to date.
Since a-IGZO can exhibit higher carrier mobility than amorphous Si, many literatures have demonstrated circuit applications. However, the typical operation frequencies of 5-stage ring oscillators are lower than 1MHz. In addition, it is hard to identify the effects of process flows to the device performance under a circuit configuration. Thus the RF performance of a single discrete device and the effect of gate dielectrics are investigated. Besides discussing the high frequency response of a-IGZO TFTs with HfO2/SiO2 bilayer dielectric, to sustain higher bias voltage, we developed Al2O3/SiO2 bilayer dielectric under the same concept. The 1.5μm gate length device can achieve fT of 384MHz and fmax of 1.06GHz, which is the fasted amorphous oxide semiconductor transistor on glass substrate to date.
GaN HEMTs have the advantages of high VBD and low Ron. However, the inherent normally-on behavior excludes GaN based HEMTs from most power electronic applications. P-GaN cap layer is demonstrated to raise the conduction band and achieve E-mode operation. Effects of process approaches、etching depth and thermal alloy temperature to threshold voltage (Vth) and operating current will be discussed. Except realizing E-mode device with operating current of 208mA/mm and Vth of 1.7V, the etching process window to achieve stable current-voltage operation was estimated to be 50±5nm for device with 60nm of p-GaN cap layer. However, a precise etching depth control of 55nm is required to achieve high VBD. A high VBD of 1630V at LGD of 16μm is successfully achieved. Base on those results, Different device and epitaxial structures were also developed to optimize the device performance, including Mo/Ti/Au gate metal, Al2O3 gate dielectric, thicker AlGaN barrier layer, different Mg concentration and double heterojunction.
At the last part, multi-finger large area power devices with total width of 30mm were developed. Two approaches were employed to realize E-mode power devices with operating current higher than 6Ampere. One is connecting depletion mode (D-mode) GaN HEMTs to Si power MOSFET and assembles this Cascode structure into a SO-8 package. The other one is p-GaN capped single chip E-mode HEMTs. Besides discussing the effects of layout and process approaches, the results of dual pulse measurements indicate that due to an additional p-GaN etching process, the current collapse effect of p-GaN capped E-mode HEMTs is severer than D-mode GaN HEMTs. However, in case of resistive load switching test with 1MHz pulse width modulation input signal, the Miller capacitance embedded in the Si power MOSFET leads to much severer input signal distortion. Thus, after improve the surface passivation process, the p-GaN capped E-mode GaN HEMTs is a promising candidate for future power electronic applications.
Subjects
氧化銦鎵鋅
薄膜電晶體
高載子遷移率電晶體
功率元件
增強型
Type
thesis
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