A novel sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation
Journal
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Pages
1117-1120
Date Issued
2010
Author(s)
Abstract
This paper describes a novel sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation which eliminates loop bandwidth limit in traditional fractional-N synthesizers. The proposed synthesizer utilizes a delay line after the reference signal to compensate phase errors and achieves at least 19dB fractional spur and quantization noise improvement if a delay line with 32ps delay resolution is employed in the phase-locked loop with 180kHz loop bandwidth at 3.5GHz synthesized frequency. The improvement can be further enhanced with advanced process with the improved delay resolution.
SDGs
Type
conference paper