A digital signal processor with programmable correlator arrayarchitecture for third generation wireless communication system

Resource

IEEE Circuits and Systems II: Analog and Digital Signal Processing 48 (12): 1110-1120

Journal

IEEE Circuits and Systems II: Analog and Digital Signal Processing

Journal Volume

48

Journal Issue

12

Pages

1110-1120

Date Issued

2001

Date

2001

Author(s)

Chen, Chi-Kuang

Tseng, Po-Chih

Chang, Yung-Chil

Chen, Liang-Gee

URI

Type

journal article

File(s)

Name

13.pdf

Size

316.54 KB

Format

Adobe PDF

Checksum

(MD5):71e4051758bae7bbb2713f349954bd70