A Single-Chip Universal Digital Satellite Receiver with 480-MHz IF input
Resource
IEEE Journal of Solid-State Circuits,34(11),1634-1648.
Journal
IEEE Journal of Solid-State Circuits
Pages
1634-1646
Date Issued
1999-11
Date
1999-11
Author(s)
Kwentus, A.Y.
Pai, P.
Jaffe, S.
Gomez, r.
Tsai, S.
Kwan, T.
Hing Tsun Hung
Shin, Y.J.
Hue, V.
Cheung, D.
Khan, R.A.
Ward, C.M.
Mong Kai Ku
Choi,K.
Searle, J.
Bult, K.
Cameron, K.
Demas, J.
Reames, C.
Samueli, H.
Abstract
This paper presents a complete single-chip universal digital satellite receiver supporting all current DBS system standards. The mixed-signal device accepts a modulated data stream at up to 90 Mbps and delivers a demodulated, error-corrected output data stream. The IC features an analog front end with 480-MHz intermediate frequency downconversion and dual 8-bit analog-to-digital converters, an all-digital BPSK/QPSK/OQPSK variable-rate receiver supporting 1-45 MBaud operation with phase/frequency recovery, variable-rate digital filters, square-root Nyquist matched filters, acquisition and tracking loops, and a DVB/DSS/DigiCipher I/II-compliant concatenated Viterbi/Reed-Solomon forward error correction decoder with on-chip deinterleaver RAM. All required clocks are generated on chip from a single reference crystal. The chip contains 1.2 million transistors in a die area of 22 mm/sup 2/ and was implemented in a single-poly 0.35-/spl mu/m CMOS process with four layers of metal.
SDGs
Type
journal article