A Multi-Modulus Divider For 24 GHz Frequency Synthesizer
Date Issued
2010
Date
2010
Author(s)
Lin, Yin-Ta
Abstract
PLL-based frequency synthesizers have been used widely in modern communication systems. The multi-modulus divider is one of the key elements in the frequency synthesizer. The desired output frequency could be derived from stable reference frequency by selecting different modulus.
This thesis presents the design and implemented of multi-modulus divider. The chips have been implemented and fabricated in 0.18μm CMOS technology. The implement of multi-modulus divider could be accomplished in three steps.
The first chip is a divider chain consists of CML and TSPC flip-flop based dividers. More design details about static divider could be learned from this chip.
The second chip is a divide-by-4/5 prescaler. Prescaler usually dominates the speed of the whole divider. A modified D flip-flop merged with NAND gate function is used in this prescaler to reduce the propagation delay.
The third chip is the whole divide-by-64~67 divider. The frequency divider is composed of three parts – a divide-by-4/5 prescaler, an asynchronous divide-by-2N counter and digital control block. The high-speed prescaler operates at high frequency, feeding the lower frequency to the low-speed counter.
The measurement results indicate that there are four division ratios could be selected. The circuit is fit for the implemented of frequency synthesizer.
Subjects
Frequency Synthesizer
Prescaler
Frequency Divider
Type
thesis
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