Metal-Only Engineering Change Order Optimization for Integrated Circuit Design
Date Issued
2014
Date
2014
Author(s)
Chang, Hua-Yu
Abstract
As the design complexity grows dramatically, late design changes are nearly in- evitable to handle specification modifications and/or rectify design errors. Metal- only engineering change order (ECO), which revises only metal layers to realize incremental design changes, is widely used in the industrial design flow. These in- cremental changes can be functional ECO, dedicated for functional rectification or specification modification, or timing ECO, dedicated for timing closure and opti- mization. In addition, to facilitate metal-only ECO, (redundant) spare cells are inserted at the early placement and routing stage. Conventionally, standard cells are regarded as spare cells. Nevertheless, these pre-inserted standard spare cells are limited by their pre-determined quantity, functionality, and locations. To overcome the inflexibility of standard cells, metal-configurable gate-array spare cells are de- veloped, and thus further enhance the practicality of metal-only ECO. To sum up, metal-only ECO becomes prevalent in the modern IC design flow to remedy late- found failures in a short turn-around time and reduce the time-to-market pressure.
In this dissertation, we propose a comprehensive solution for metal-only ECO. First, for metal-only ECO using standard spare cells: 1) We propose a stable match- ing based functional metal-only ECO synthesizer that can resolve spare cell com- petition and does not sacrifice timing and routability. 2) Different from negative slack and gate delay used in most prior work, we propose a new metric of timing criticality, fixability, by considering the smoothness of timing violating paths, and using the B ́ezier curve as the golden path to measure the smoothness of a path. Furthermore, in order to concurrently fix timing violations, we derive a propagation property to divide violating paths into independent segments. 3) We observe that separating functional and timing ECO may fail to fix all timing violations. Con- sequently, we present the first work to perform simultaneous functional and timing ECO. We use an augmented bipartite graph to model both types of ECO.
Second, we address a new problem of ECO optimization using metal-configurable gate-array spare cells. We first study the properties of this new ECO problem, pro- pose a new cost metric, aliveness, to model the capability of a spare gate array, and then develop two ECO optimization algorithms—functional ECO and timing ECO using metal-configurable gate-array spare cells. 1) For the new timing ECO, we con- sider aliveness, routability, and timing satisfaction in our framework to fully utilize the capability of spare arrays. Then, we resort to iterative mixed integer linear pro- gramming (MILP) in our timing ECO framework, where a set of independent and small MILPs are computed. 2) For the new functional ECO, we observe that this functional ECO problem has the nature of dynamic logical and physical costs for selecting spare gate arrays. Unlike existing functional ECO works, which perform technology mapping based on ECO patches, we perform reverse mapping from spare gate arrays to handle these dynamic costs. Then, we devise a spare array relation graph to record geometrical adjacency among spare gate arrays and interleave with the AIG network of ECO patches.
Subjects
實體設計
設計變更
時序修正
技術映射
陣列元件
Type
thesis
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